Pour les temps d'acces, d'apres le site de samsung:
200MHz Clock, 400Mbps data rate.
166MHz Clock, 333Mbps data rate.
VDD= +2.6V ± 0.10V, VDDQ= +2.6V ± 0.10V
VDD= +2.5V ± 0.20V, VDDQ= +2.5V ± 0.20V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
Four banks operation
Differential clock inputs(CK and /CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs
- Read latency 3 (clock) for DDR400
- Read latency 2/2.5 (clock) for DDR 200/266/333
- Burst length (2, 4, 8)
- Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
LDM,UDM for write masking only (x16)
DM for write masking only (x8)
DM for write masking only (x4, x8)
Auto & Self refresh
7.8us refresh interval(4K/64ms refresh)
Maximum burst refresh cycle : 8
TC/LB3: 66pin TSOP(II) package
NC/LB3: 54pin sTSOP(II)-300 package
GC/LB3: 60 ball FBGA package
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Clan Torysss.