LIBRARY ieee ;
use std.textio.all;
USE ieee.std_logic_1164.all ;
LIBRARY std;
ENTITY russel IS
PORT ( init1,init2 : IN STD_LOGIC;
acquit: OUT STD_LOGIC );
END russel ;
ARCHITECTURE testTableau OF russel IS
file table_entree : text open READ_MODE is "d:\russell\table_entree.txt";
file table_sortie : text open WRITE_MODE is "d:\russell\table_sortie.txt";
SIGNAL val_1FromFile : integer;
SIGNAL val_2FromFile : integer;
SIGNAL val_3FromFile : integer;
SIGNAL val_4FromFile : integer;
SIGNAL val_5FromFile : integer;
BEGIN
PROCESS (init1,init2)
variable val_1 : integer;
variable val_2 : integer;
variable val_3 : integer;
variable val_4 : integer;
variable val_5 : integer;
variable writ : integer;
constant val : natural := 2;
BEGIN
if init1 = '1' then
acquit <='1';
readline (table_entree,ligne_1);
read (ligne_1,val_1);
readline (table_entree,ligne_2);
read (ligne_2,val_2);
readline (table_entree,ligne_3);
read (ligne_3,val_3);
readline (table_entree,ligne_4);
read (ligne_4,val_4);
readline (table_entree,ligne_5);
read (ligne_5,val_5);
val_1fromfile <= (val_1*val);
val_2fromfile <= (val_2*val);
val_3fromfile <= (val_3*val);
val_4fromfile <= (val_4*val);
val_5fromfile <= (val_5*val);
else acquit<='0';
end if;
if init2 ='1' then
write (array_1, val_1fromfile);
writeline (table_sortie, array_1);
write (array_2, val_2fromfile);
writeline (table_sortie, array_2);
write (array_3, val_3fromfile);
writeline (table_sortie, array_3);
write (array_4, val_4fromfile);
writeline (table_sortie, array_4);
write (array_5, val_5fromfile);
writeline (table_sortie, array_5);
else acquit<='0';
end if;
END PROCESS;
END testTableau;